Verification of systems-on-chips using genetic evolutionary test techniques from a software applications perspective.

Abstract

This thesis examines verification of system-on-a-chip (SoC) designs using a software applications test methodology that is enhanced by genetic evolutionary test generations and functional coverage. The verification methodology facilitates application based testing using behavioural simulations before the chip is fabricated. The goal of the methodology is to verify commonly used real-life functionalities of the SoC earlier in the design process, so as to uncover design bugs that are considered most critical to actual SoC usages when the SoC is employed in its intended end-product. The verification methodology is based on a test building blocks approach, whereby many different components of various SoC application use-cases are extracted into building blocks, and then recomposed with other components to construct greater variety and range of test cases for verifying the SoC. An important facet of the methodology is to address automated creation of these software application test cases in an effective and efficient manner. The goal is to maximise test coverage and hence bug detection likelihood using minimal verification resources and effort. To this end, test generations techniques employing single and multi objective genetic algorithms and evolutionary strategies are devised in this thesis. Using coverage and test size to drive test generations, test suites which are continually evolved to enhance SoC verifications are created, thereby achieving automated coverage driven verifications. Another enhancement for test generation is to select the input test creation parameters in an analytical manner. A technique using Markov chains is developed to model and analyse the test generation method, and by doing so, test parameters can be selected to achieve desired verification characteristics and outcomes with greater likelihood. To quantify verification effectiveness, a functional coverage method is formulated. The coverage method monitors attributes of the SoC design during testing. The combinations of attribute values indicate the application functionalities carried out. To address the coverage space explosion phenomenon for such combinatorial methods and facilitate the coverage measurement process, partial order domains and trajectory checking techniques from the formal verification field of symbolic trajectory evaluation are adopted. The contributions of this thesis are a verification platform and associated tool-suite that incorporates the software applications test methodology, algorithmic test generation, and functional coverage techniques.