Design of a direct downconversion receiver for IEEE802.11a WLAN.

Abstract

Wireless communication technologies are no longer limited for voice band applications, but have entered the era for multimedia data link. The IEEE802.11 family, which occupies a bandwidth in the multi-mega hertz region with the highest data rate of 54 Mbps, now has become the most widely deployed wireless LAN standards. The rapid adoption of IEEE802.11 for computer wireless networks and their growing popularity in mobile applications highlight the need for a low cost, low power consumption, and monolithic solution. To meet this challenge, traditional RF techniques, which revolved around the superheterodyne architecture can no longer be used. On the contrary, new receiver frontend architectures need to be developed to satisfy the demand of system level integration. Direct downconversion receivers directly translate the RF spectrum to the baseband by setting the LO frequency equal to the RF. Due to the single frequency translation, expensive and bulky off-chip filters and 50 ohm I/O matching networks at IF are no longer required. Also, the single-stage quadrature mixers further simplify the receiver design and reduce the power dissipation. Subsequent baseband components and ADCs are also possible to be integrated with the RF frontend to achieve a monolithic receiver chip. Despite the previously mentioned advantages, the implementation of a direct downconversion receiver has its own set of performance challenges. In particular, the performance is plagued by DC offset, flicker noise, linearity and mismatches etc. The main objective of this project is to investigate the feasibility of using direct downconversion architecture for the IEEE802.11a standard, and implement the design in a 0.18 µm CMOS technology. By approaching the design issue at a theoretic point of view, extensive modeling and simulations based on a SIMULINK IEEE802.11a physical layer theme have been carried out to evaluate the receiver performance. SER results of the receiver demonstrate that the impairments associated with zero IF can be minimised to an acceptable level. Under the guidance of the system level analysis, the circuit level design of a monolithic direct downconversion receiver has been implemented in a 0.18 µm RF CMOS process, including the building blocks of an LNA, mixer, baseband amplifier and a channel-selection filter. Particularly, a novel LNA design methodology with an improved noise figure and less power consumption has been developed. The mixer conversion gain and phase noise have been analysed by a novel approach. The combination topology of the highpass DC offset removal filter and the baseband amplifier provids the best linearity with a negligible noise figure degradation. Circuit simulations are performed using the foundry provided RF design kit with enhanced noise models to capture the extra noise of passive and deep submicron devices. Circuit level simulations show a qualified receiver frontend for the IEEE802.11a standard. As data converters are important building blocks in wireless receivers, research on high performance Sigma-Delta modulators is also included. MATLAB based programs have been developed for both the discrete and continuous time transfer function synthesis. A BPSDM chip with variable centre frequencies has been developed to verify the SDM transfer function algorithm and the design methodology. The design of an ultra fast continuous time SDM is particularly focused on for a broadband data conversion. To alleviate the challenge of the comparator speed limit, a novel noise transfer function with a unit clock delay has been synthesised. With such a delayed transfer function, a three-stage comparator can be acheieved that solves the comparator gain and speed tradeoff. The full chip simulation shows an acceptable performance for the IEEE802.11a standard.