Please use this identifier to cite or link to this item:
https://hdl.handle.net/2440/69095
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Type: | Conference paper |
Title: | Memristor-based synaptic network and logical operations using in-situ computing |
Author: | Kavehei, O. Al-Sarawi, S. Cho, K. Iannella, N. Kim, S. Eshraghian, K. Abbott, D. |
Citation: | Proceedings of the 7th International Conference on Intelligent Sensors, Sensor Networks and Information Processing (ISSNIP 2011), held in Adelaide, Australia, December 6-9 2011: pp.137-142 |
Publisher: | IEEE |
Publisher Place: | CD |
Issue Date: | 2011 |
ISBN: | 9781457706738 |
Conference Name: | Intelligent Sensors, Sensor Networks and Information Processing (7th : 2011 : Adelaide, Australia) |
Statement of Responsibility: | Omid Kavehei, Said Al-Sarawi, Kyoung-Rok Cho, Nicolangelo Iannella, Sung-Jin Kim, Kamran Eshraghian, Derek Abbott |
Abstract: | We present new computational building blocks based on memristive devices. These blocks, can be used to implement either supervised or unsupervised learning modules. This is achieved using a crosspoint architecture which is an efficient array implementation for nanoscale two-terminal mem-ristive devices. Based on these blocks and an experimentally verified SPICE macromodel for the memristor, we demonstrate that firstly, the Spike-Timing-Dependent Plasticity (STDP) can be implemented by a single memristor device and secondly, a memristor-based competitive Hebbian learning through STDP using a 11000 synaptic network. This is achieved by adjusting the memristor's conductance values (weights) as a function of the timing difference between presynaptic and postsynaptic spikes. These implementations have a number of shortcomings due to the memristor's characteristics such as memory decay, highly nonlinear switching behaviour as a function of applied voltage/current, and functional uniformity. These shortcomings can be addressed by utilising a mixed gates that can be used in conjunction with the analogue behaviour for biomimetic computation. The digital implementations in this paper use in-situ computational capability of the memristor. © 2011 IEEE. |
Rights: | © 2011 IEEE |
DOI: | 10.1109/ISSNIP.2011.6146610 |
Description (link): | http://www.issnip.org/~issnip2011/index.htm |
Published version: | http://dx.doi.org/10.1109/issnip.2011.6146610 |
Appears in Collections: | Aurora harvest 7 Electrical and Electronic Engineering publications |
Files in This Item:
File | Description | Size | Format | |
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hdl_69095.pdf | Accepted version | 974.47 kB | Adobe PDF | View/Open |
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