Adelaide Research & Scholarship
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https://hdl.handle.net/2440/32191
| Type: | Conference paper |
| Title: | A mapping technique for the synthesis of linear threshold gate networks used to implement Boolean functions |
| Author: | Celinski, P. Sherman, G. Lopez, J. Abbott, D. |
| Citation: | Proceedings of the 2001 WSES International Conference, 2001 / Mastorakis, N. (ed./s), pp.4251-4255 |
| Publisher: | World Scientific and Engineering Society |
| Publisher Place: | CD-ROM |
| Issue Date: | 2001 |
| ISBN: | 9608052254 |
| Conference Name: | WSES International Conference (11 Feb 2001 : Tenerife, Canary Islands, Spain) |
| Editor: | Mastorakis, N. |
| Statement of Responsibility: | P Celinski, GD Sherman, D Abbott |
| Appears in Collections: | Aurora harvest 6 Electrical and Electronic Engineering publications |
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