Please use this identifier to cite or link to this item: https://hdl.handle.net/2440/2382
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dc.contributor.authorAl-Sarawi, S.-
dc.contributor.authorAbbott, D.-
dc.contributor.authorFranzon, P.-
dc.date.issued1998-
dc.identifier.citationIEEE Transactions on Advanced Packaging, 1998; 21(1):2-14-
dc.identifier.issn1070-9894-
dc.identifier.urihttp://hdl.handle.net/2440/2382-
dc.description.abstractThis paper reviews the state-of-the-art in three-dimensional (3-D) packaging technology for very large scale integration (VLSI). A number of bare dice and multichip module (MCM) stacking technologies are emerging to meet the ever increasing demands for low power consumption, low weight and compact portable systems. Vertical interconnect techniques are reviewed in details. Technical issues such as silicon efficiency, complexity, thermal management, interconnection density, speed, power etc. are critical in the choice of 3-D stacking technology, depending on the target application, are briefly discussed. © 1998 IEEE.-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleA review of 3-D packaging technology-
dc.typeJournal article-
dc.identifier.doi10.1109/96.659500-
pubs.publication-statusPublished-
dc.identifier.orcidAl-Sarawi, S. [0000-0002-3242-8197]-
dc.identifier.orcidAbbott, D. [0000-0002-0945-2674]-
Appears in Collections:Aurora harvest 2
Electrical and Electronic Engineering publications

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