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|Title:||Asynchronous control circuit design and hazard generation : inertial delay and pure delay models / by Nozard Tabrizi.|
|School/Discipline:||Dept. of Electrical and Electronic Engineering|
|Abstract:||Investigates two level logic synthesis of asynchronous circuits from signal transition graphs (STGs) under the inertial gate delay model and the well behaved environment. Focuses on design methodologies and hazard free implementations based on redundant logic where the inertial delay model does not help to avoid hazards.|
|Dissertation Note:||Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1997|
Asynchronous circuits Design and construction.
|Description:||Bibliography: leaves 158-167.|
xvii, 173 leaves ; 30 cm.
|Provenance:||This electronic version is made publicly available by the University of Adelaide in accordance with its open access policy for student theses. Copyright in this thesis remains with the author. This thesis may incorporate third party material which has been used by the author pursuant to Fair Dealing exception. If you are the author of this thesis and do not wish it to be made publicly available or If you are the owner of any included third party copyright material you wish to be removed from this electronic version, please complete the take down form located at: http://www.adelaide.edu.au/legals|
|Appears in Collections:||Research Theses|
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|01front.pdf||185.02 kB||Adobe PDF||View/Open|
|02whole.pdf||9.05 MB||Adobe PDF||View/Open|
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