Please use this identifier to cite or link to this item: https://hdl.handle.net/2440/106931
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Type: Journal article
Title: Unbiased finite-memory digital phase-locked loop
Author: You, S.
Pak, J.
Ahn, C.
Shi, P.
Lim, M.
Citation: IEEE Transactions on Circuits and Systems, Part 2: Express Briefs, 2016; 63(8):798-802
Publisher: IEEE
Issue Date: 2016
ISSN: 1549-7747
1558-3791
Statement of
Responsibility: 
Sung Hyun You, Jung Min Pak, Choon Ki Ahn, Peng Shi, and Myo Taeg Lim
Abstract: Digital phase-locked loops (DPLLs) have been commonly used to estimate phase information. However, they exhibit poor performance or, occasionally, a divergence phenomenon, if noise information is incorrect or if there are quantization effects. To overcome the weaknesses of existing DPLLs, we propose a new DPLL with a finite-memory structure called the unbiased finite-memory DPLL (UFMDPLL). The UFMDPLL is independent of noise covariance information, and it shows intrinsic robustness properties against incorrect noise information and quantization effects due to the finite-memory structure. Through numerical simulations, we show that the proposed DPLL is more robust against incorrect noise information and quantization effects than the conventional DPLLs are.
Keywords: Digital phase-locked loop (DPLL); finite-memory structure; unbiasedness
Description: Date of publication February 18, 2016; date of current version July 28, 2016
Rights: © 2016 IEEE.
DOI: 10.1109/TCSII.2016.2531138
Grant ID: http://purl.org/au-research/grants/arc/DP140102180
http://purl.org/au-research/grants/arc/LP140100471
http://purl.org/au-research/grants/arc/LE150100079
Published version: http://dx.doi.org/10.1109/tcsii.2016.2531138
Appears in Collections:Aurora harvest 8
Electrical and Electronic Engineering publications

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